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Rebellions introduces REBEL-Quad, the world’s first UCIe-Advanced AI accelerator designed for peta-scale inference. Built for efficiency at every layer, REBEL-Quad redefines the economics of AI data centers—delivering higher throughput and lower power consumption compared to GPU-based systems. This session will feature a demo showcase, highlighting how REBEL-Quad brings frontier-class performance into production, enabling enterprises to scale large-model workloads without the energy tax. Join us to see how next-generation chiplet architecture translates into real customer value: efficiency, scalability, and faster time-to-deployment.

Author:

Jinwook Oh

Co Founder and CTO
Rebellions

Jinwook Oh is the Co-Founder and Chief Technology Officer of Rebellions, an AI chip company based in South Korea. After earning his Ph.D. from KAIST (Korea Advanced Institute of Science and Technology), he joined the IBM TJ Watson Research Center, where he contributed to several AI chip R&D projects as a Chip Architect, Logic Designer, and Logic Power Lead. At Rebellions, he has overseen the development and launch of two AI chips, with a third, REBEL, in progress. Jinwook's technical leadership has been crucial in establishing Rebellions as a notable player in AI technology within just three and a half years.

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Jinwook Oh

Co Founder and CTO
Rebellions

Jinwook Oh is the Co-Founder and Chief Technology Officer of Rebellions, an AI chip company based in South Korea. After earning his Ph.D. from KAIST (Korea Advanced Institute of Science and Technology), he joined the IBM TJ Watson Research Center, where he contributed to several AI chip R&D projects as a Chip Architect, Logic Designer, and Logic Power Lead. At Rebellions, he has overseen the development and launch of two AI chips, with a third, REBEL, in progress. Jinwook's technical leadership has been crucial in establishing Rebellions as a notable player in AI technology within just three and a half years.

Following the MLCommons MLPerf Inference v5.1 Results on the morning of Tuesday 9th September on the keynote stage, Miro Hodak, Senior Member of Technical Staff, AI Performance Engineering at AMD will deliver a detailed analysis of the results followed by a Q&A session from the audience. 

Author:

Miro Hodak

Senior Member of Technical Staff, AI Performance Engineering
AMD

Miro Hodak is a Principal Member of Technical Staff at AMD, where he focuses on AI performance and benchmarking. Prior to joining AMD, he served as an AI Architect at Lenovo and was a professor in physics at North Carolina State University before that. 

Miro has been actively involved with MLPerf and MLCommons since 2020, contributing to the development of multiple MLPerf benchmarks and submitting results across several rounds of Inference and Training. Since 2023, he has served as co-chair of the MLPerf Inference Working Group.

He has authored peer-reviewed publications in fields ranging from artificial intelligence and computer science to materials science, physics, and biochemistry, with his work cited over 2,500 times.

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Miro Hodak

Senior Member of Technical Staff, AI Performance Engineering
AMD

Miro Hodak is a Principal Member of Technical Staff at AMD, where he focuses on AI performance and benchmarking. Prior to joining AMD, he served as an AI Architect at Lenovo and was a professor in physics at North Carolina State University before that. 

Miro has been actively involved with MLPerf and MLCommons since 2020, contributing to the development of multiple MLPerf benchmarks and submitting results across several rounds of Inference and Training. Since 2023, he has served as co-chair of the MLPerf Inference Working Group.

He has authored peer-reviewed publications in fields ranging from artificial intelligence and computer science to materials science, physics, and biochemistry, with his work cited over 2,500 times.

Distributed training jobs are brittle; a single node failure can halt progress and waste expensive GPU cycles. This technical demo dives into Cluster Director, focusing on how engineers can automate resilient, large-scale GPU infrastructure. We'll start with a declarative YAML configuration to define and provision a multi-node GPU cluster, optimized with the ideal network topology for NCCL communication. The core of the demo will be a live failure simulation. You will see Cluster Director automatically detect a preempted node, perform remediation, and maintain the integrity of the running workload with minimal disruption.

Author:

Ilias Katsardis

Senior Product Manager
Google Cloud

Ilias Katsardis is a Senior Product Manager based in Sunnyvale, CA, driving the future of AI infrastructure at Google Cloud. He is responsible for Cluster Director and the Cluster Toolkit, two key components of Google's supercomputing architecture. Passionate about making large-scale AI and HPC more accessible, Ilias focuses on creating solutions that automate complex configurations and provide a seamless user experience. His work enables researchers and developers to spend less time on infrastructure management and more time on scientific breakthroughs. With a rich background that includes roles at Cray Inc. and ClusterVision, along with founding two tech startups, Ilias brings over 15 years of deep industry expertise to his role.

... read more

Ilias Katsardis

Senior Product Manager
Google Cloud

Ilias Katsardis is a Senior Product Manager based in Sunnyvale, CA, driving the future of AI infrastructure at Google Cloud. He is responsible for Cluster Director and the Cluster Toolkit, two key components of Google's supercomputing architecture. Passionate about making large-scale AI and HPC more accessible, Ilias focuses on creating solutions that automate complex configurations and provide a seamless user experience. His work enables researchers and developers to spend less time on infrastructure management and more time on scientific breakthroughs. With a rich background that includes roles at Cray Inc. and ClusterVision, along with founding two tech startups, Ilias brings over 15 years of deep industry expertise to his role.

Author:

Abhijith Prabhudev

Product Manager
Google Cloud

Abhijith Prabhudev is a Product Manager based in Sunnyvale, CA, leading the AI infrastructure observability and monitoring at Google Cloud. He is responsible for GPU infrastructure reliability, monitoring and resiliency capabilities. His work enables researchers and developers to spend less time on infrastructure management and more time on building and training AI models. With over 15+ years of infrastructure industry experience that includes leading VMware vSphere product team and a full stack engineer, Abhijith is passionate about solving infrastructure problems that hinder developer and administrator productivity. 

... read more

Abhijith Prabhudev

Product Manager
Google Cloud

Abhijith Prabhudev is a Product Manager based in Sunnyvale, CA, leading the AI infrastructure observability and monitoring at Google Cloud. He is responsible for GPU infrastructure reliability, monitoring and resiliency capabilities. His work enables researchers and developers to spend less time on infrastructure management and more time on building and training AI models. With over 15+ years of infrastructure industry experience that includes leading VMware vSphere product team and a full stack engineer, Abhijith is passionate about solving infrastructure problems that hinder developer and administrator productivity. 

Large language models can now power capable software agents, yet real‑world success comes from disciplined engineering rather than flashy frameworks. Most reliable agents are built from simple, composable patterns instead of heavy abstractions.

The talk will introduce patterns to add complexity and autonomy only when it pays off. Attendees should leave with a practical decision framework for escalating from a single prompt to multi‑step agents, also keeping in mind guardrails for shipping trustworthy, cost‑effective agents at scale. 

Author:

Sushant Mehta

Research Engineer
Google Deepmind
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Sushant Mehta

Research Engineer
Google Deepmind

Author:

Sherman Ikemoto

Group Director
Cadence

Sherman Ikemoto is the Sales Development Group Director at Cadence Design Systems, where he leads global business development for the innovative Reality DC Digital Twin solution. With a passion for addressing challenges in data center design, performance, and sustainability, Sherman brings extensive expertise to the forefront of this critical industry. Previously, Sherman served as Managing Director and Board Member at Future Facilities, the pioneer of the original data center Digital Twin, and as North America Sales and Marketing Director at Flomerics, where he helped introduce computational fluid dynamics modeling to electronics cooling design. During his tenure at Future Facilities, Sherman was a sought-after speaker at prominent industry events like ITW, Data Center World, Uptime Symposium, and Data Center Dynamics. Sherman holds a Bachelor of Science in Mechanical Engineering (BSME) from San Jose State University, where he was a member of the Tau Beta Pi engineering honor society, and a Master of Science in Mechanical Engineering (MSME) from Santa Clara University. His career reflects a deep commitment to advancing sustainable and efficient technologies for the data center industry.

... read more

Sherman Ikemoto

Group Director
Cadence

Sherman Ikemoto is the Sales Development Group Director at Cadence Design Systems, where he leads global business development for the innovative Reality DC Digital Twin solution. With a passion for addressing challenges in data center design, performance, and sustainability, Sherman brings extensive expertise to the forefront of this critical industry. Previously, Sherman served as Managing Director and Board Member at Future Facilities, the pioneer of the original data center Digital Twin, and as North America Sales and Marketing Director at Flomerics, where he helped introduce computational fluid dynamics modeling to electronics cooling design. During his tenure at Future Facilities, Sherman was a sought-after speaker at prominent industry events like ITW, Data Center World, Uptime Symposium, and Data Center Dynamics. Sherman holds a Bachelor of Science in Mechanical Engineering (BSME) from San Jose State University, where he was a member of the Tau Beta Pi engineering honor society, and a Master of Science in Mechanical Engineering (MSME) from Santa Clara University. His career reflects a deep commitment to advancing sustainable and efficient technologies for the data center industry.